Job Details:
Job Description:
The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industrydefining analog and mixedsignal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. As a senior analog design engineering manager, you will lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology. This engineering manager role will be responsible for the following: • Technical Leadership: Guiding the design of analog circuits (e.g., ADCs/DACs, Phase Interpolators, voltage regulators) and ensure high-quality silicon through all phases of planning, tech readiness, pre-silicon design, and post-silicon validation. Enabling engineers to focus on high ROI activities by driving efficiency throughout the development cycle, including the adoption of automated and AI-supported solutions. • Project Management: Create detailed execution plans, manage schedules, resources, dependencies, and deliverables to meet IP milestones and SOC TI deadlines. Use data to articulate progress, results, and to guide next steps. • Team Management and Development: Hire, develop, and mentor a team of analog design engineers with skillsets ranging from introductory to senior analog leads. Direct report team will be located in the US and will be about 10-15 engineers. This role is also expected to direct the work of, grow, and give feedback for team members from the broader org who are working on projects led by this manager. • Cross-functional Collaboration: Partner with IP leads across domains (architecture, logic, physical design and layout), with key SOC design team members, and with post-silicon validation teams throughout the IP design and productization lifecycle. You should also expect to work daily with peer design teams and partners located in both the US and globally. • Culture and Work Environment: This leader must drive results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. This is an on-site role and you are expected to work in the office at least 4 days per week.
Qualifications:
Minimum Qualifications • Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 12+ years of experience • 8+ years in a management or leadership role • Proven expertise in analog IP development and delivering from concept to launch. • Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity. • Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits. • Excellent communication, documentation, and presentation skills to audiences ranging from individual contributors to technical leaders and executives. Preferred Qualifications • PhD or Master's degree in Electrical Engineering, Electronics Engineering, or related field. • 12+ years in a management or leadership role • 8+ years of experience managing analog IP design teams. • Hands-on design experience in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, Transmitter (TX) design, or Receiver (RX) design. • Deep knowledge of high speed serial IO technologies such as PCIe/CXL and USB Type C and of die to die technologies such as UCIe. • 10+ years of proven success building, leading, and driving execution in silicon teams delivering to complex, high-impact programs.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, Oregon, Hillsboro
Business group:
The Central Engineering Group (CEG) is Intel's >
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
