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Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
Drive block and top-level EMIR/electrical verification closureWork on power grid design, construction, and implementation using existing infrastructures and where necessary, creating custom solutions in PNR tool environmentWork multi-functionally with CAD/EDA vendors to ensure fidelity of analysis results with methodology teams to cover unique use cases, with implementation teams to drive design and sign-off closure, and with the SOC level teams to meet IP delivery quality and schedulePreferred QualificationsExperience implementing high-performance and low-power VLSI designs
Experience with SAPR/PNR design flow infrastructure
Understanding of challenges related to latest deep sub-micron technology
Produce impactful design fixes and automate wherever possible, spanning multiple tool domains in physical construction and analysis
Working knowledge of industry standard tools like Apache Redhawk and Cadence Voltus as well as PNR implementation, layout tools, verification, and STA
Strong communication and presentation skills to regularly summarize the state of the design and drive design convergence across multiple blocks and teams in a timely fashion
Minimum QualificationsMinimum BS and 10+ years of relevant industry experience
Experience with silicon level power delivery, electromigration, and IR drop analysis
Experience with scripting of SAPR or EMIR flow automation for the efficient processing of large scale design and analysis data, debugging of issues, and isolating design sensitivities
