Job Details:

Job Description:

• Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

• Participates in the definition of architecture and microarchitecture features of the block being designed.

• Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Supports SoC customers to ensure high quality integration of the IP block.

Qualifications:

• Candidate must have a Bachelor, Master or PhD Degree in Computer Engineering, Electrical Engineering, Computer Science or related field.

• Candidate will have 15 years of hands on experience with mixture of Logic Design and or PreSiliconVerification or DFX design.

Candidate must possess strong fundamentals on the following area.

• Good understanding in SV, OVM, UVM and verification methodologies

• Experience in using verification tools such as VCS DVE Verdi etc

• Extensive coding experience that includes logic, behavioral modelling, SV coding

• Strong fundamental knowledge of HW description language Verilog and assertion coding and logic simulation

• Strong in problem solving debugging various simulation failures and formal verification

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's >

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.