High‑Speed RTL Design Engineer

Key Responsibilities

High‑SpeedRTL Design & Implementation

• Design and implementtiming‑criticalRTL blocks, including:

• Control and sequencing FSMs

• Power‑up, shutdown, andmode‑transitionlogic

• Register banks and configuration logic

• Telemetry and monitoringdatapath

• Develop RTL with attention tolatency, deterministic behavior,race‑freelogic, and metastability avoidance.

Nanometer‑Process‑AwareRTL Coding

• Write RTL that is robust to:

• Tight setup and hold margins

• Clock skew and uncertainty

• Multi‑cycleandfalse‑pathconstraints

• Process, voltage, and temperature (PVT) variation

• Ensure RTL isclean for synthesis, static timing analysis, and ECO cyclesin sophisticated technology nodes.

Clocking, Reset &Power‑AwareLogic

• Implement and reviewclock‑domaincrossings (CDC)using proven synchronization techniques.

• Designreset and initialization logicto ensure predictable system startup and recovery.

• Supportpower‑awareandmode‑dependentbehavior as the need arises by system operation.

Integration & Debug

• Integrate RTL blocks into larger subsystems ortop‑leveldesigns, resolving:

• Port‑listmismatches

• Clock and reset dependencies

• Mode interaction issues

• Debug RTL and integration issues using simulation waveforms and tool feedback.

Verification & Timing Closure Support

• Work closely with verification engineers to:

• Clarify design intent and corner cases

• Fix RTL issues uncovered during verification

• Address timing issuesidentifiedduring synthesis orplace‑and‑routebyrefining logic, simplifying control paths, or adding limited pipelining under guidance.

Design Reviews & Documentation

• Participate actively inRTL and design reviews, incorporating feedback from senior engineers.

• Maintainclear documentationdescribing block functionality, assumptions, and known limitations.

Required Technical Skills

RTL & Digital Design

• StrongproficiencyinSystemVerilog/ Verilog RTL
  

Experience with:

• FSM design and implementation

• Reset synchronization

• Clock‑domaincrossing concepts

• Solid understanding oftiming‑criticalcontrol logic.

High‑Speed& System Awareness

Solid understanding of:

• Setup/hold timing fundamentals

• Critical‑pathsensitivity

• Multi‑mode and settings‑based behavior

• Exposure tomixed‑signalinteraction(digital logic controlling or responding to analog behavior).

Flow Awareness

• Familiarity with:

• RTL lint and CDC checks

• Synthesis and basic STA reports

• DFT‑friendlyRTL practices

• UPF and LEC

• Ability to debug issues exposed duringRTLsign‑offor late integration stages.

Good‑to‑Have or equivalent experience

• Experience withPMICs,mixed‑signalSoCs, or companion ICs

• Exposure to industry-standard specifications

• Basic scripting skills (Python /Tcl) for automation

• Experience working acrossRTL–DV–PD handshakes

Behavioral Expectations

• Works independently on assigned RTL modules or subsystems

• Raises risks early with analysis and proposed solutions

• Demonstrates growing ownership of RTL quality and delivery

• Learns from reviews and feedback to deepenhigh‑speeddesignexpertise

• Effective and compliant use of Micron‑approved AI tools to augment verification activities, improve execution efficiency, and support continuous improvement.