Job Details:

Job Description:

We are looking for highly passionate new talents to work on industry leading DDR PHY design as Logic Design Engineer.

You will be contributing to Intel family of products on the latest process and create the world-changing technology. You will be responsible for:

• Internal IP RTL design/development.

• Implement new features, change requests and improvements on existing features for the IP.

• Drive and ensure IP handoff quality assurance and compliance. Define power intent strategy, handling of signals crossing power planes and clock domains; along with other FE collateral for integration.

• Perform design exercise, collaborate with verification and structural design teams for functional/feature/integration validation and physical design implementation.

• Perform FE Quality checks in various logic design aspect ranging from RTL static checks to RTL synthesizability check, timing/power convergence, netlist quality check, Formal Equivalent Verification and many more.

Qualifications:

Candidates should have a minimum of a Bachelor or Master Degree in Electrical and Electronic or Computer Science Engineering.

Knowledge in one or more of the following domains:

• IP/Subsystem architecture, I/O architecture, industry standard high speed bus protocols

• Industry exposure and knowledge of design methodology

• Proficient in RTL design using Verilog/System Verilog

• Knowledge in industry FE/RTL tools and design methodologies

• Able to commit to a minimum 3-month internship

Job Type:

Student / Intern

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's >

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.