
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Lead Micron’s workload-driven memory architecture and performance strategy across mobile and server-class platforms, shaping the future of DRAM, LPDDR, and HBM based memory systems. Own the end-to-end vision for workload characterization, benchmarking, and performance modeling, translating real-world application behavior into next-generation memory architecture, product features, and ecosystem innovations. Drive cross-organizational alignment spanning silicon, controllers, firmware, OS, hyperscalers, and industry partners, establishing Micron as a leader in workload-informed memory design.
Role Type: DMTS/SMTS
Domain: Memory Systems Architecture, Workload Analysis, Performance Engineering for servers and mobiles.
Key Responsibilities
Benchmarking & Workload Characterization
Define the industry-leading benchmarking framework for Mobile(Geekbench, PCMark, MLPerf Mobile, real app traces etc) and Server( SPEC CPU, SPECrate, STREAM, MLPerf, database/cloud workloads)
Characterize, Memory bandwidth, latency, QoS, tail latency, Access patterns (locality, working set, read/write mix), NUMA behavior, cache interaction, memory-level parallelism
Define and maintain representative workload suites for customer scenarios
Root Cause Analysis & Optimization
Lead deep dives using PMU counters, perf, eBPF, ftrace, ARM Streamline / VTune equivalents
Identify bottlenecks in Memory controller scheduling, DRAM timing and row-buffer locality, Cache/memory interaction
Drive optimizations across, Kernel (NUMA, huge pages, memory policies), Firmware / BIOS tuning, Application-level performance tuning
Architecture & System-Level Innovation
Drive system-leveltradeoffanalysis (performance, power, cost, scalability) to guide product decisions.
Influencememory controller policies (scheduling, QoS, fairness) and the evolution of heterogeneous/tiered memory hierarchies.
Modeling & Predictive Analytics
Establish advanced frameworks for performance modeling, analytical simulation, and trace-driven workload replay at scale.
Lead what-if exploration for future workloads (AI-first systems) and scaling across memory configurations (channels, ranks, interleaving, bandwidth).
Translate models into product requirements, performance targets, and customer-facing guidance.
Cross-Stack Optimization
Drive end-to-end optimizations across application → OS → firmware → hardware stack.
Influence Linux kernel memory management (NUMA, huge pages, scheduling), data placement, and memory tiering strategies.
Partner with ecosystemteams tooptimize AI frameworks, databases, and virtualization platforms for memory efficiency and performance.
Minimum Qualifications
15–24+ years in memory systems, performance engineering, or system architecture.
Proven expertise in workload analysis and workload characterization at scale for servers and mobiles.
Strong programming experience: Python, C/C++, and system-level tooling.
Deep experience with benchmarking suites (SPEC, MLPerf, STREAM, and real-world workloads) and Linux performance tools (perf, eBPF, PMU-based profiling).
Demonstrated impact on architecture decisions and product roadmaps through cross-functional leadership.
Ideal Attributes
Visionary thinker who connects workload trends → architecture → product strategy.
Strong analytical, modeling, and target="_blank">hrsupport_india@micron.com
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