MTS Silicon System Architect

Key Responsibilities

Architecture & Technical Ownership

• Define and own IP architecture and micro‑architecture for complex digital IP blocks
• Translate system‑level and customer requirements into scalable and efficient architectural solutions
• Develop and maintain architecture specifications and ensure alignment across implementation teams
• Drive architectural reviews and provide guidance on performance, area, power, and scalability trade‑offs
  

Design Execution & Quality

• Provide technical leadership from architecture definition through IP release
• Partner with design and verification teams to:
  • Review micro‑architecture and RTL implementation
  • Validate test plans and coverage strategy
  • Debug functional, integration, and customer issues
• Support SoC integration, bring‑up, and post‑silicon debug activities as needed
  

Interfaces & System Integration

• Architect and support IPs involving common SoC interfaces and data paths, such as:
  • DMA and data‑movement engines
  • Interconnect and control interfaces
  • Networking and security‑related datapath
• Ensure clean integration with system fabrics and surrounding IPs
  

Collaboration in a Multi-Functional Environment

• Collaborate with planning, software, validation, and system teams to support product needs
• Participate in IP roadmap and feature discussions
• Mentors and provide technical direction to senior engineers and designers
  

Required Qualifications

Education

• Master’s or Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Experience

• Proven experience (15+ years) in ASIC / SoC design with significant focus on IP architecture or technical leadership
• Proven experience owning IPs from concept through tape‑out or production release
• Prior experience in senior technical or lead design roles

Technical Skills

Architecture & Design

• IP architecture and micro‑architecture definition
• RTL design and ASIC design flow understanding
• Power‑on, integration, and debug exposure

Interfaces & Protocols

• Experience with standard SoC interfaces (e.g., interconnects, control buses, high‑speed interfaces)

Tools & Methodologies

• RTL design and review
• Lint, CDC, synthesis, and timing closure flows
• Hardware description languages (e.g., SystemVerilog)
• Scripting to invent/debug automation is encouraged

Preferred Qualifications

• Experience with reusable IP development across multiple products or platforms
• Background in high-throughput or target="_blank">hrsupport_india@micron.com

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