NoC Design Verification Engineer

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most >

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

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Job Description:

Responsibilities

• Develop and execute verification plans for NoC and coherent interconnect IP/subsystems

• Build UVM/SystemVerilog-based verification environments, testbenches, checkers, scoreboards, assertions, and functional coverage

• Verify multiple NoC configurations, topologies, routing scenarios, and protocol interactions

• Create assertions, checkers, and coverage aligned with evolving NoCLink specifications and configuration requirements

• Drive verification for subsystem integration involving memory fabrics, cache/coherency paths, and large SoC interconnects

• Partner with design and architecture teams to review specifications and convert them into actionable test plans

• Debug simulation failures, isolate root cause, and work with RTL/design teams on closure

• Track verification progress using metrics such as coverage, bug trends, and testplan completion

• Contribute to development of VIP/interfaces and reusable DV components for interconnect verification

• Support regression bring-up, test triage, and verification closure activities

Required Qualifications

• 4+ years of experience with a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field

• Strong experience in Design Verification using SystemVerilog and UVM

• Experience verifying interconnects, NoCs, memory subsystems, cache/coherency logic, or large SoC subsystems

• Good understanding of verification methodologies including test planning, constrained-random verification, assertions, coverage, and regression debug

• Experience writing SVA/assertion-based checks and functional coverage models

• Strong debugging skills across RTL, testbench, and simulation environments

• Solid understanding of computer architecture and on-chip data movement

Preferred Qualifications

• Experience with coherent interconnects, NoC fabrics, or memory fabrics

• Familiarity with protocol/interface verification and VIP development

• Experience with subsystem- or SoC-level verification in multicore or high-performance designs

• Exposure to performance, stress, corner-case, and configuration-based verification

• Familiarity with scripting using Python, Perl, or shell

• Experience collaborating across global design and DV teams

What You’ll Work On

• Verification of NoCLink-related functionality across different configurations

• Development of assertions/checkers/coverage for updated NoC specifications

• Support for VIP/interface definition work, signal dependency understanding, and configuration-driven verification

• Verification strategy and execution for scalable on-chip communication fabrics

Nice to Have

• Experience with formal verification, CDC-related verification planning, or protocol compliance checking

• Understanding of cache coherency and high-bandwidth data paths

• Prior experience in CPU, subsystem, or SoC verification environments

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in: