Senior PCB Layout Engineer

Senior PCB Layout EngineerThis role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Job Description:

Senior PCB Layout Engineer

A Senior PCB Layout Engineer is a technical expert responsible for designing complex, high-speed printed circuit boards using the Cadence Design SystemsAllegro PCB Designer platform. This role focuses on advanced constraint-driven layout, signal integrity awareness, manufacturing readiness, and automation (often with SKILL), while leading critical hardware projects.

Role Summary

Design and deliver high-performance, multi-layer PCBs for complex electronic systems such as networking equipment, servers, telecom hardware, aerospace systems, or high-speed embedded platforms. The engineer works closely with hardware, SI/PI, mechanical, and manufacturing teams to ensure first-pass success and production readiness.

Key Responsibilities

Advanced PCB Layout

• Design complex boards (12–40+ layers) using Cadence Allegro PCB Designer
• Perform optimized component placement for:
  • High-speed digital
  • Power distribution
  • Thermal performance
  • EMI control
• Route critical interfaces:
  • DDR4/DDR5
  • PCIe Gen4/Gen5+
  • USB 3.x / Type-C
  • Ethernet (10G–112G SerDes)
• Implement:
  • Differential pair routing and tuning
  • Length and phase matching
  • Controlled impedance structures

Constraint & Stackup Management

• Define and manage rules using Constraint Manager
• Develop stackups with controlled impedance and fabrication feasibility
• Work with PCB vendors to validate materials, via structures, and HDI capability

Signal Integrity & Power Integrity Awareness

• Apply SI/PI best practices:
  • Return path continuity
  • Crosstalk reduction
  • Proper decoupling strategy
• Collaborate with SI/PI teams
• Implement simulation-driven layout changes

HDI and Advanced Technologies

• Blind/buried vias and microvias
• BGA escape for high pin-count devices
• Backdrilling for high-speed signals
• High-current and low-noise power routing

Manufacturing & NPI Support

• Generate fabrication and assembly outputs:
  • ODB++, IPC-2581, Gerber
  • Drill files, drawings, stackup documentation
• Perform DFM/DFA reviews with vendors
• Support prototype builds and resolve manufacturing issues

Leadership

• Mentor junior and mid-level PCB designers
• Lead layout planning and design reviews
• Estimate schedules and manage multiple projects

Required Qualifications

• 8–15+ years of PCB layout experience
• Expert proficiency in Cadence Allegro
• Strong knowledge of:
  • High-speed design techniques
  • Impedance control and stackup planning
  • HDI technologies
  • EMI/EMC fundamentals
• Solid understanding of PCB fabrication and assembly processes

Preferred (High-End Systems)

• Networking, server, or telecom hardware experience
• Familiarity with:
  • 25G/56G/112G SerDes
  • Backplane design
  • Thermal/mechanical co-design
• Experience with SI/PI analysis tools

Typical Impact

• Enables first-pass board success (fewer respins)
• Supports higher data rates and system reliability
• Improves team efficiency through automation
• Serves as the technical authority for PCB layout

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

#unitedstates

#networking

Job:

Engineering

Job Level:

TCP_03The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 105,500 - 213,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered.

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

Recruitment Fraud Alert

We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.

All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.