Senior Staff Engineer, Physical Design - NoC

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most >

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Job Description:

About the Role --
At SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Sr Staff Physical Design Engineer (NoC/Uncore), you will own and drive the implementation of massive, high-bandwidth interconnects and Uncore subsystems across multiple products from RTL to GDSII. You will be responsible for implementing and collaborating on the co-design of PPA-optimized solutions, focusing on achieving high-performance and power efficiency using the latest technology nodes.

While your primary focus will be physical design, this role requires you to operate fluidly across design-abstraction layers. You will act as a crucial bridge between architecture, RTL, and implementation, relying on deep backend expertise and system-level understanding to influence top-level architecture and micro-architecture. Your work will directly impact the scalability, bandwidth, and quality of our IP, in addition to implementation PPA.

Responsibilities - What you’ll do

• Lead NoC Implementation: Drive the complete physical design implementation for complex NoC and Uncore sub-systems, including synthesis, place & route, and signoff.

• Drive Cross-Abstraction-Layer Co-Design: Go beyond standard physical design implementation by actively engaging in Architecture/RTL/PD co-design. Understand the IP micro-architecture deeply enough to suggest RTL modifications, pipeline strategies, or architectural tweaks that resolve physical bottlenecks early.

• Solve NoC-Specific Challenges: Tackle complex physical bottlenecks unique to interconnects, long-distance timing closure, repeater/pipeline-stage insertion, and top-level clock distribution/methodology across massive die areas.

• Architectural Floorplanning: Drive top-level floorplanning, macro placement, hierarchical partitioning, and pin assignments to optimize data flow between CPU cores, accelerators, and memory boundaries.

• Aggressive PPA Optimization: Optimize implementation for aggressive PPA goals, managing trade-offs and optimizing design points for various high-performance product lines.

• Cross-Functional Leadership: Collaborate heavily with architecture, RTL, and power teams to drive co-design closure. Influence micro-architecture decisions early in the design cycle to prevent physical bottlenecks.

• Drive Methodology: Architect, support, and significantly improve physical design flows, automation, and methodology for top-level integration and hierarchical implementation across multiple technology nodes.

• Mentorship: Act as a technical pillar within the team, mentoring junior engineers and leading by example in driving process efficiency and design excellence.

Requirements - What you’ll bring

• 10+ years of hands-on experience in physical design implementation. Understanding of design, architecture and PPA tradeoffs are a plus.

• Cross-Abstraction-Layer Expertise (Highly Desired): A strong understanding of digital logic design, NoC micro-architecture, and system-level data flow is a major plus. You should be comfortable reading RTL; and engineering across abstraction layers to drive PPA optimization through architecture/design/implementation co-design.

• NoC/Uncore Expertise: Proven experience in physical design implementation of massive interconnects, coherent hubs, or complex memory subsystems. Familiarity with NoC architectures and the physical implications of high-bandwidth bus routing.

• Hierarchical Mastery: Deep expertise in top-level physical integration, hierarchical P&R methodologies, and global timing closure.

• Advanced Problem Solving: Proven ability to optimize for aggressive PPA targets using advanced physical design techniques, accompanied by a detail-oriented mindset and clear communication skills.

• Tool Proficiency: Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence synthesis, PnR and signoff implementation tools.

• Education: Bachelor’s or Master’s in Electrical or Computer Engineering.

Why join us?

• Be part of the RISC-V movement and help define the future of computing architecture.

• Work on industry-leading IP adopted by top customers and shipped in high volumes worldwide.

• Collaborate with world-class engineers in a supportive, fast-paced, learning environment.

• Enjoy a culture that values innovation, ownership, and technical excellence.

• Our large IP portfolio offers opportunities to engineer solutions across multiple IPs and product families over time.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in: