SerDes System Validation Engineer

In this highly visible role, you will actively work within Analog-Mixed/Signal design team and participate in validation and debug of embedded circuits; collaborating with many subject areas to enable the world's premiere products. You will closely work with a talented group of Analog-Mixed/Signal designers working diligently to deliver hard IPs to Apple's products while exceeding the highest expectations of quality, innovation and efficiency! At Apple, we work every single day to craft products that enrich people's lives. And in doing so face great challenges as SOC/PHY design complexity continues to increase. If you have strong fundamentals and a track record of tackling technical challenges. If you are inspired by your curiosity and eagerness to learn new skills and to improve the value and impact of your work. If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems. If you love working with people and teams with multifaceted strengths to accomplish great things. If you like fire-fighting when challenges occur while keeping a phenomenal team spirit. If you care about society and have demonstrated leadership skills through dedication to great causes. We have an opportunity for a forward-thinking and especially hardworking system validation engineer with strong background in high speed serial links. As a member of our dynamic team, you will have the rare and rewarding opportunity to work on upcoming products that will surprise and delight millions of Apple's customers every day! And all of this while enjoying a great culture where you own your career.

Description

Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in system. Work with design teams to understand the architecture and define DFT needs to help improve testability and first time silicon success. Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic.","responsibilities":"Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying and qualify all operations, analyzing robustness and margins in system.

Work with design teams to understand the architecture and define DFT needs to help enhance testability and first-time silicon success.

Be involved in mixed-signal verification tasks to assure Pre Silicon test coverage and robustness. Drive testability features for in situ Validation and Debug.

Preferred Qualifications

The ideal candidate should have experience in high-speed serial links with expertise in the following:

Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters.

Solid understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques.

Solid understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops).

Hands-on experience to drive lab and production testing, debug, and data analysis.

Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization.

Skills in scripting and automation to enhance efficiency are highly desirable.

Experience in high-speed serial links, with knowledge of common high-speed SerDes protocols like PCIe, USB, DP, and MPHY.

Knowledge of Tx/Rx equalization techniques and circuits, including CTLE, DFE, and de-emphasis, as well as CDR architectures and implementations.

Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired.

Exposure to firmware assisted mixed signal IP development is desirable.

Knowledge and inquisitiveness in AI/ML domains, and ability to apply the concepts for improved silicon performance, and also for productivity improvements in the design/validation of the IP.

Minimum Qualifications

BS and 10 +years of relevant industry experience.

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