Staff Design Verification Infrastructure Engineer - VIPs and Testbench

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most >

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

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Job Description:

Join SiFive’s Design Verification Infrastructure team to develop and maintain the Verification Platform VIPs, AIPs, and other testbench components used across SiFive. An ideal candidate will be a strong Design Verification engineer with a solid understanding of software engineering. You will be expected to collaborate with Design Verification engineers to develop reusable testbench components and integrate them within SiFive’s Chisel-based Verification Platform..

Responsibilities:

• Architect, develop, and maintain the Verification Platform to provide a common infrastructure that scales with the growth of SiFive for Design Verification and other verification and validation activities

• Develop Verification Platform libraries for expressing verification intent in Scala with Chisel, including test harnesses, stimulus, scoreboards, and other generators

• Develop Verification Platform VIPs, AIPs, and other testbench components using System Verilog, UVM, and other related technologies

• Develop Verification Platform test plans and testbenches to verify and release testbench components with high quality

• Educate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform

Requirements:

• Design Verification experience with System Verilog and UVM

• Experience designing and verifying VIPs, AIPs, and other testbench components

• Understanding of modern software engineering practices

• Typically 7+ years with BS/MS/PhD in EE/CE/CS or related field.

Desired:

• Experience with Chisel, Scala, and/or Python

• Understanding of EDA tools and flows for Design Verification

• Familiarity with DevOps practices, build systems, and CI / CD

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in: